1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device with a trench gate power MOSFET construction that is used in a power supply circuit or the like, and to a method of manufacturing the same.
2. Background Art
Trench gate power MOSFETs have been widely used in recent years in a variety of power supply apparatuses, such as DCxe2x80x94DC converters. FIGS. 51A and 51B show one example of a semiconductor device that has a trench gate power MOSFET construction according to the background art, with FIG. 51A being an overhead view of the semiconductor device and FIG. 51B being a cross-sectional view taken along the line Axe2x80x94A in FIG. 51A. In these drawings, numerals 100a to 100e are cells, numeral 110 is a trench, numeral 111 is a gate electrode film, numeral 117 is an N+ type silicon substrate, numeral 118 is an Nxe2x88x92 epitaxial layer, numeral 119 is a P type body layer, numeral 120 is a P+type dispersion region, numeral 121 is an N+type source region, numeral 122 is an interlayer dielectric, numeral 124 is a source electrode film, numeral 125 is a drain electrode film, numeral 127 is a gate insulating film, and numeral 141 is an upper insulating film.
As shown by the cells 100a to 100e in FIG. 51A, the present semiconductor device is formed with a large number of cells that are arranged in a hound""s-tooth check-like pattern on the surface of the semiconductor device. As shown by cell 100a, for example, each cell is formed with an N+type source region 121 surrounding a P+type dispersion region.
As shown in FIG. 51B, the cross-sectional form of the present semiconductor device is such that an Nxe2x88x92 epitaxial layer 118 is formed on top of an N+ type silicon substrate 117, with a P type body layer 119 being formed on top of the Nxe2x88x92 epitaxial layer 118. P+type dispersion regions 120 and N+type source regions 121 are formed in this P type body layer 119. Trenches 110 that pass through the P type body layer 119 and are deep enough to reach into the Nxe2x88x92 epitaxial layer 118 are also formed between the cells 100a to 100e. 
The trenches 110 provide an opening to the P type body layer 119 and reach into the Nxe2x88x92 epitaxial layer 118. A gate insulating film 127 is formed on the side surfaces and bottom surfaces of these trenches 110, with a gate electrode film 111 being formed in the spaces surrounded by the gate insulating film 127. An upper insulating film 141 is formed on top of the gate insulating film 127 and the gate electrode film 111. An interlayer dielectric 122 is also formed on top of the upper insulating film 141 and parts of the N+type source region 121.
A source electrode film 124 is formed on top of the P+type dispersion region 120, the N+ type source region 121, and the interlayer dielectric 122. A drain electrode film 125 is also formed on the other surface of the N+ type silicon substrate 117.
In a semiconductor device of the above construction, when a voltage is applied between the source electrode film 124 and the drain electrode film 125 and a voltage that is equal to or greater than a predetermined threshold voltage is simultaneously applied between the gate electrode film 111 and the source electrode film 124, an inversion layer is formed in the P type body layer 119 in a boundary region adjacent to the gate insulating film 127, thereby creating a channel. As a result, an electric current flows through this channel from the drain electrode film 125 to the source electrode film 124.
On the other hand, with a semiconductor device of the above construction, the trenches 110 have to be deeply formed in order to make the bottom parts of the gate insulating film 127 thicker than the other parts and so ensure that a suitable withstand voltage is achieved for the gate insulating film 127. For this purpose, as shown in FIG. 51B, the trenches 110 are produced with a large depth D so as to provide sufficient space for making the bottom parts of the gate insulating film 127 thick. If the trenches 110 are deeply formed, an increase can be made in the area of the outer surface of the gate insulating film 127, making it possible to reduce the On resistance Ron.
However, when the area of the outer surface of the gate insulating film 127 is increased, this also results in an increase in the capacitance Crss between the gate electrode film 111 and the Nxe2x88x92 epitaxial layer 118, which worsens the switching characteristics of the semiconductor device. Also, increasing the depth D can lead to problems such as an electrical field being concentrated at a specific part of the gate insulating film 127 when a voltage is applied between the source electrode film 124 and the drain electrode film 125.
To solve the problems mentioned above, the present invention has an object of providing a semiconductor device for which the capacitance between the gate electrode film and the drain layer can be reduced while keeping the On resistance low and the withstand voltage of the gate insulating film at a sufficient level.
To achieve the stated object, the present invention is a semiconductor device, including: a semiconductor substrate, in which a drain layer of a first conductivity type and a conductive region of an opposite conductivity-type to the first conductivity type are formed with the conductive region over the drain layer; a trench formed as an opening in the conductive region that reaches the drain layer; a source region of the first conductivity type that is positioned inside the conductive region, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench so that an upper surface of the gate insulating film at a bottom of the trench is deeper than the source region but is shallower than an interface between the drain layer and the conductive region; a gate electrode film that is formed on inner surfaces of the gate insulating film; and a source electrode film that is insulated from the gate electrode film and is connected to the source region.
As a result, in the semiconductor device of the present invention, the gate electrode film is formed at a shallower position than the interface between the drain layer and the conductive region, so that even if trenches are made shallower than in the background art, the bottom part of the gate insulating film can still be made about as thick as in the background art. Also, as a reduction can be made in the surface area of the outer surfaces of the gate electrode film, the capacitance can be reduced. Also, since the bottom part of the gate insulating film can be made thick even when the trenches are shallower than in the background art, it is possible to avoid problems, such as a concentration of an electric field at a specific part of the gate insulating film, that occur when the trenches are formed deeper than the drain layer. It should be noted that the gate electrode film should be preferably formed with a depth that is sufficient and results in the On resistance being low.
The present invention is also a semiconductor device, including: a semiconductor substrate, in which a drain layer of a first conductivity type and a conductive region of an opposite conductivity-type to the first conductivity type are formed with the conductive region being positioned over the drain layer; a trench formed as an opening in the conductive region that reaches the drain layer; a source region of the first conductivity type that is positioned inside the conductive region, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench so that parts of the gate insulating film that are located beyond a predetermined depth are thicker than other parts of the gate insulating film; a gate electrode film that is formed on inner surfaces of the gate insulating film; and a source electrode film that is insulated from the gate electrode film and is connected to the source region.
With the semiconductor device of the present invention, parts of the gate electrode film that are located beyond a predetermined depth are thinner than other parts of the gate insulating film, which is to say, the parts of the gate electrode film that are shallower than the predetermined depth. As a result, the capacitance of the periphery of the deep part of the gate electrode film can be suppressed and the On resistance can be reduced by a certain amount.
The predetermined depth may be in a range that is deeper than the source region but is shallower than an interface between the drain layer and the conductive region.
The present invention is also a semiconductor device, comprising: a semiconductor substrate, in which a drain layer of a first conductivity type, and a conductive region of an opposite conductivity-type to the first conductivity type are formed with the conductive region being positioned over the drain layer; a trench formed as an opening in the conductive region that reaches the drain layer; a source region of the first conductivity type that is positioned inside the conductive region, with at least part of the source region being exposed to inner surfaces of the trench; a gate insulating film that is formed on the inner surfaces of the trench, the gate insulating film being formed so that a thickness of the gate insulating film decreases towards the opening in the conductive region; a gate electrode film that is formed on inner surfaces of the gate insulating film; and a source electrode film that is insulated from the gate electrode film and is connected to the source region.
With the semiconductor device of the present invention the gate electrode film is formed so that a part located beyond a predetermined depth is thinner than other parts, which is to say, the parts that are shallower than the predetermined depth. As a result, the capacitance of the periphery of the deep part of the gate electrode film can be suppressed and the On resistance can be reduced by a certain amount.
Further, a method of manufacturing a semiconductor device comprises the steps of forming a first silicon oxide film on a surface of a semiconductor substrate on which a drain layer of a first conductivity-type has been formed, forming an opening at a predetermined position in the silicon oxide film to expose the drain layer, forming an opening in the exposed drain layer to form a trench in the drain layer, forming a second silicon oxide film on the surface of the semiconductor substrate and inner surfaces of the trench, removing the second silicon oxide film from the surface of the semiconductor substrate and inner surfaces of the trench, so as to let the second silicon oxide film remain up to a predetermined depth in the bottom part of the trench, forming a third silicon oxide film on inner surfaces of the trench by oxidizing the surface of the semiconductor substrate in the area of the trench, depositing a polysilicon film on the surface of the semiconductor substrate and the inner surfaces of the trench, so as to fill up the trench, removing the polysilicon film from the surface of the semiconductor substrate and part of the trench, removing the third silicon oxide film from the surface of the semiconductor substrate and part of the inner surfaces of the trench; and forming a fourth silicon oxide on the surface of the semiconductor substrate and the inner surfaces of the trench.
Accordingly, because the trench is filled up by depositing a polysilicon film after carrying out thermal oxidation with the second silicon oxide film remaining up to a predetermined depth in the bottom part of the trench, a gate electrode can be easily obtained that is shallower than the surface between a drain layer and the conductive region. Therefore, while forming a trench shallower than prior art trenches, a film thickness of the bottom surface of the gate insulating film as thick or thicker than the prior art film thicknesses can be achieved. Further, as the surface area of the outer surfaces of the gate electrode film can be kept small, the capacitance can be reduced. Furthermore, problems such as an electrical field being concentrated at a specific part of the gate electrode film can be resolved because while forming the trench shallower than prior art trenches, the thickness of the bottom part of the gate electrode can be made thick, and therefore the trench can be formed deeper than the drain layer.
Also, a method of manufacturing a semiconductor device, comprising the steps of: forming a first silicon oxide film on a surface of a semiconductor substrate on which a drain layer of a first conductivity-type has been formed; forming an opening at a predetermined position in the silicon oxide film to expose the drain layer; forming an opening in the exposed drain layer to form a first trench in the drain layer; forming a second silicon oxide film on the surface of the semiconductor substrate and inner surfaces of the first trench; forming a silicon nitride film that covers the surface of the semiconductor substrate and the inner surfaces of the first trench; removing the silicon nitride film from the surface of the semiconductor substrate and a bottom surface of the first trench, so as to expose the second silicon oxide film at the surface of the semiconductor substrate and at the bottom surface of the first trench; removing at least part of the first silicon oxide layer and the second silicon oxide layer, as well as the silicon oxide layer exposed at the bottom surface of the first trench, so as to expose the drain layer at the bottom surface of the first trench; forming a second trench by forming an opening in the drain layer exposed at the bottom surface of the first trench; oxidizing the drain layer in a periphery of the second trench; removing a second silicon oxide film and the silicon nitride film from inner side surfaces of the first trench; forming a third silicon oxide film on inner surfaces of the first trench and the second trench and on the surface of the semiconductor substrate; depositing a polysilicon film on the inner surfaces of the first trench and the second trench and the surface of the semiconductor substrate, so as to fill up the first trench and the second trench; removing the polysilicon film from the surface of the semiconductor substrate and part of the first trench; removing the third silicon oxide film from the surface of the semiconductor substrate and part of the inner surfaces of the first trench; and forming a fourth silicon oxide on the surface of the semiconductor substrate and the inner surfaces of the first trench.
As a result, a second trench can be formed in a bottom part of the first trench, thereby making it possible to form a gate electrode film with upper parts and lower parts of different thicknesses.